The present invention relates to a large scale integrated circuit device (LSI device) used in, e.g., an information processing apparatus and, more particularly, to an LSI device capable of reducing power consumed inside the LSI.
Conventionally, not so many schemes to reduce LSI power consumption of this type have been proposed. So all data signals operating on a system bus are applied to an LSI chip through a bidirectional buffer, and consequently internal circuits of the LSI operate even when the operations are not required inside the LSI chip. This results in unnecessary power consumption.
In the above conventional LSI design, data are wasted, for no control is performed to apply data signals operating on the system bus only when they are required inside the LSI. For this reason, power tends to be consumed inside the LSI chip in accordance with switching between high (H) and low (L) of a data signal on the system bus. This process is used in most of LSI designs. In particular, a CMOS system wastes power if an unnecessary operation is performed because the system originally consumes large power.